1. Field of Invention
The present invention relates to a thin-film transistor (TFT), and more specifically, relates to an improved art of TFT transistor characteristics.
2. Description of Related Art
The various devices which use TFTs can include active matrix liquid display devices. For instance, FIG. 11(A) shows an active matrix liquid crystal display device that is formed on a transparent substrate, such as glass, and having a roughly central region that is identified as a picture display region 81. In this picture display region 81, picture elements are formed into sections by data lines 90 and scanning lines 91 composed of a metal film, such as aluminum, tantalum, molybdenum, titanium and tungsten, a silicide film, a conductive semiconductor film, or the like. In each picture element, a liquid crystal unit 94 (liquid crystal cell) is formed where picture signals are input through a TFT 30 for picture switching. To the data lines 90, a data-side drive circuit 60 is constructed that includes a shift register 84, a level shifter 85, video lines 87 and analog switches 86. To the scanning lines 91, scanning-side drive circuits 70 are constructed that have a shift register 88 and a level shifter 89. In each picture element, a holding capacitor 40 is formed between the scanning line 91 and a capacity line 92 extending parallel thereto. The holding capacitor 40 has a function to improve the holding characteristics of charge at the liquid crystal units 94. This holding capacitor 40 is sometimes formed between the scanning line 91 of the front stage and a picture element electrode.
At the data-side and the scanning-side drive circuits 60 and 70, respectively, a CMOS circuit is constructed with an N type TFT 10 and a P type TFT 20 as shown in FIG. 11(B). Such CMOS arrangement is used to implement an inverter circuit, etc. with more than one or two stages at the drive circuits 60 and 70.
Therefore, on the active matrix substrate 200, three types of TFTs are formed on the surface of the substrate that include an N type TFT 10 for the drive circuit, a P type TFT 20 for the drive circuit and an N type TFT 30 for picture element switching. However, these TFTs 10, 20 and 30 have a common structure. Thus, in order to avoid redundancy of explanation, the structure of the N type TFT 10 for the drive circuit, as well as the manufacturing method thereof, will be explained with reference to FIG. 12, FIG. 13, FIG. 14 and FIG. 15.
As illustrated in FIG. 12, on the active matrix substrate 200, a bedding protective film 51 made of a silicon oxide film is formed at the surface side of the substrate 50. On the surface of this bedding protective film 51, a polycrystal semiconductor film 100 is formed that is patterned into island forms. On the surface of the semiconductor film 100, a gate insulating film 12 is formed, and a gate electrode 14 is formed on the surface of this gate insulating film 12. In the semiconductor film 100, a channel region 15 is formed at a region facing the gate electrode 14 through the gate insulating film 12. At the sides of this channel region 15, a high concentration source region 16 and a high concentration drain region 17 are formed in a self-aligned condition relative to the gate electrode 14. To the high concentration source region 16 and high concentration drain region 17, a source electrode 41 and a drain electrode 42 are electrically connected respectively through contact holes in an interlayer insulating film 52.
In order to manufacture the TFT 10 with such a structure, first, a substrate made of glass, etc. is cleaned by ultrasonic cleaning or the like as in FIG. 13 (A). Subsequently, as shown in FIG. 13 (B), a bedding protective film 51 is formed over the entire surface of the substrate 50 under the conditions of a substrate temperature from about 150 to 450xc2x0 C.
Thereafter, as illustrated in FIG. 13 (C), a semiconductor film 100 is formed on the surface of the bedding protective film 51. At this time, by applying a low temperature process, the substrate 50 made of glass is prevented from being thermally deformed. A low temperature process indicates that the maximum temperature in the process (the maximum temperature wherein the temperature of a substrate as a whole increases at the same time) is lower than about 600xc2x0 C. (preferably, less than about 500xc2x0 C.). On the contrary, a high temperature process indicates that the maximum temperature of the process (the maximum temperature wherein the temperature of a substrate increases as a whole at the same time) is higher than about 600xc2x0 C. This involves carrying out a high temperature procedure at 700-1,200xc2x0 C. such as film-formation under high temperature and thermal oxidation of silicon.
However, since it is impossible to form a polycrystal semiconductor film directly on the substrate in the low temperature process as explained later, this semiconductor film 100 should be crystallized after an amorphous semiconductor film 100 is formed first by a plasma CVD method or a low pressure CVD method. Methods such as the Solid Phase Crystallization (SPC) method and Rapid Thermal Annealing (RTA) method for instance, are included as this crystallization method. As shown in FIG. 13 (D), by carrying out laser annealing wherein excimer laser beams using XeCl are irradiated (ELA: Excimer Laser Annealing/crystallization process), the rise in substrate temperature is restrained, and polycrystal Si with a large grain diameter is also provided.
In this crystallization process, laser beams (excimer laser) from a laser beam source 320, for example, are irradiated toward the substrate 50 that is placed on a stage 310 through an optical system 325 as shown in FIG. 14. In this process, line beams L0 wherein an irradiation range L is long in an X direction (for example, line beams at 200 Hz of laser pulse cyclic frequencies) are irradiated onto the semiconductor film 100, and the irradiation region L is shifted in a Y direction. The beam lengths of the line beams L0 are 400 mm herein, and the output intensity thereof is, for instance, 300 mJ/cm2. Also, in shifting the irradiation region L of laser beams in the Y direction, the line beams are scanned so as to overlap sections with 90% of the peak laser intensity in the width direction per region. As a result, the amorphous semiconductor film 100 is melted once, and is then polycrystallized after a cooling and solidifying process. In this process, the irradiation period of laser beams to each region is extremely short and the irradiation region L is local relative to the substrate as a whole, so that the substrate 50 as a whole is not heated to a high temperature at the same time. Thus, even though the glass substrate used as the substrate 50 is inferior to a quartz substrate in heat resistance, deformation, cracks, etc. are not formed by heat.
Next, as shown in FIG. 13 (E), the polycrystal semiconductor film 100 is patterned in island forms by the photolithography technique.
Next, as illustrated in FIG. 15 (A), a gate insulating film 12 made of a silicon oxide film is formed at the surface side of the semiconductor film 100.
Next, as shown in FIG. 15 (B), a conductive film 140 containing aluminum, tantalum, molybdenum, titanium, tungsten, etc. is formed by a sputtering method. After forming a resist mask 301 on the surface of the conductive film 140, as shown in FIG. 15 (C), the conductive film 140 is patterned and a gate electrode 14 is then formed as shown in FIG. 15 (D).
Next, as illustrated in FIG. 15 (E), phosphorus ions are introduced at the dosage of about e.g., 1xc3x971015 cmxe2x88x922 to the semiconductor film 100 with the gate electrode 14 as a mask. As a result, a source region 16 and a drain region 17 are formed in the semiconductor film 100 in a self-aligned condition relative to the gate electrode 14 and at the high concentration of about 1xc3x971020 cmxe2x88x923 in impurity concentration. The section in the semiconductor film 100 where the impurities are not introduced becomes a channel region 15.
After forming an interlayer insulating film 52 as shown in FIG. 12, annealing is carried out for activation. Then, after contact holes are formed in the interlayer insulating film 52, a source electrode 41 and a drain electrode 42 are formed.
In an N type TFT constructed as mentioned above, drain voltage that is positive relative to the potential of the source electrode 16 is applied to the drain electrode 42 as in FIG. 16 (A), and positive gate voltage is applied to the gate electrode 14. As a result, negative electric charge concentrates on the interface of the channel region 15 and the gate insulating film 12, forming an N type channel 151 (inversion layer). At this time, when drain voltage is small enough relative to gate voltage, the source region 16 and the drain region 17 are connected by the channel 151, so that drain electric current increases as drain voltage (non-saturation region) rises as indicated with a solid line L0 in the transistor characteristics (current-voltage characteristics) shown in FIG. 17. On the contrary, as drain voltage increases to where it almost equals the gate voltage, induced electron density near the drain region becomes small as shown in FIG. 16 (B), thus causing a pinch-off. Under this condition, even if drain voltage is increased higher than that level, drain electric current does not increase and becomes almost constant (at the saturation region) as indicated with the solid line L0 in FIG. 17. The current value in this case is called saturation current. Thus, if the TFT 10 is driven by applying this saturation region, constant drain current can be obtained, thus preventing the TFT 10 itself and peripheral circuits from being damaged by excess current.
As described above, the transistor characteristics of a TFT are basically dominated by the behavior of plural carriers (electrons in case of the N type, and holes in case of the P type). However, when drain voltage becomes high, a phenomenon (Kink effect) is found wherein the above-noted drain current, which should be constant, abnormally increases. The reason will be explained below. First, as drain voltage becomes high and an electric field between the source and the drain intensifies at the TFT, carriers are accelerated by this electric field and will have a lot of energy. The carriers are accelerated from the source region 16 towards the drain region 17, so that they will have the maximum energy near the drain region 17. The carriers with large energy (hot carriers) collide against the atoms in the semiconductor film and impurity atoms, thus generating pairs of electrons and holes. The generated holes, as shown in FIG. 16 (C), increase the potential of the channel region 15, and electric current in response to the injection of the holes mentioned above flows from the channel region 15 to the source region 16. Such a phenomenon can be considered by relating the channel region 15 to a base, the source region 16 to an emitter and the drain region 17 to a collector respectively. The electric current by holes flowing from the channel region 15 to the source region 16 can be considered as base current. The electric current flowing from the source region 16 to the drain region 17 in response to the electric current flowing from this channel region 15 to the source region 16 can be considered as collector electric current. Therefore, this phenomenon is also called bipolar action. With such bipolar transistor type behavior (bipolar action), drain current increases sharply (Kink effect) even at the saturation region as drain voltage rises in the case of a conventional TFT as indicated with a two-dot chain line L1 in FIG. 17. As a result, there is a danger that the TFT 10 itself and the peripheral circuits would be damaged by excess current. In addition, such a phenomenon will be clear as the ON-state current level of the TFT 10 rises by increasing the degree of crystallization of the semiconductor film 100, so that the reliability tends to decline at a higher ON-state current level in the case of a conventional TFT 10.
Therefore, the objectives of the present invention are to reduce the bipolar transistor type behavior and to present a TFT that can stabilize saturation current and improve reliability.
In order to solve the problem mentioned above, in a thin-film transistor 10 wherein a channel region 15 facing a gate electrode 14 through a gate insulating film 12 and source and drain regions 16 and 17 connected to the channel region 15 are formed in a semiconductor film 100 on the surface of an insulating substrate 50 as illustrated in FIG. 16 (D), the present invention is characterized in that a recombination center 150 is formed in the above-noted channel region 15 for capturing carriers.
The operation and effects of the TFT of the present invention are explained by referring to an N type TFT as an example, even if drain voltage becomes high and hole/electron pairs are generated by hot carriers, these holes and electrons are recombined and captured at the recombination center 150 formed in the channel region 15. As a result, as holes are injected into the source region 16 from the channel region 15, hole density would not become high, so that the injection of electrons from the source region 15 to the channel region 15 due to this hole-injection will not occur. Thus, there are no fluctuations in saturation current resulting from the bipolar transistor type behavior mentioned above. As a result, in the case of the TFT of the present invention, as illustrated with a dotted line L2 or a one-dot chain line L3 in FIG. 17, drain current will not increase sharply even if drain voltage fluctuates at the saturation region. Therefore, TFT itself and peripheral circuits will not be damaged by excess current, etc., thus improving reliability.
In the present invention, it is preferable that the recombination center concentrates at a location near the drain region in the channel region. For example, in the channel region, the recombination center preferably concentrates at a region that is separated only at a distance equivalent to ⅓ or {fraction (1/10)} of the channel length from the drain region.
In the present invention, the recombination center can be formed by impurities introduced to the channel region or by crystal defects. In this case, the impurities are at least one kind of impurity selected from the group consisting of inert-gas, metals, Group III elements, Group IV elements and Group V elements.
In the present invention, the density of the recombination center is preferably within the range from 1xc3x971013 cmxe2x80x943 to 1xc3x971020 cmxe2x88x923. Also, a carrier-capturing cross section at the recombination center is preferably within the range from 1xc3x971013cm2 to 1xc3x9710xe2x88x9220 cm2.
In the present invention, a structure wherein the recombination center concentrates on the side where the gate electrode is located in the direction of thickness of the channel region, or a structure wherein the recombination center concentrates on the side opposite to the side where the gate electrode is located in the direction of thickness of the channel region may be adopted.